Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about
benefits at Google.
Responsibilities
- Define, plan and execute end-to-end physical package substrate design of mobile SOC packages as a unique contributor, meeting performance/power/area requirements.
- Manage and drive co-design initiatives across silicon, package, and system levels, including securing production sign-off for package designs.
- Participate in the development of new silicon Internet Protocols (IPs) and packaging technology through system requirement analysis, feasibility studies and package test vehicle designs.
- Collaborate closely with Signal integrity (SI)/Power Integrity (PI), Test, New Product Introduction (NPI) and Mechanical Engineering teams to refine and optimize product package architecture and design. Develop, implement and debug package design methodology and CAD flow.
- Interface with packaging suppliers, ensuring package design and Bill of Materials (BOM) documentation meets requirements for high volume manufacturing.
Minimum qualifications:
- Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
- 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs.
- Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production.
- Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in package outline, package routing strategy, bump and ball grid array (BGA) assignment, netlist management.
- Experience in package design intercept of new packaging technologies and new silicon interfaces/subsystems.
- Experience in physical verification flow development (e.g., Layout Versus Schematic (LVS), Design Rule Checking (DRC), connectivity).
- Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD).
Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; San Diego, CA, USA.