Senior Silicon Architect

The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google.

Position reports to the Google Mountain View, CA office & may allow for a hybrid schedule as per Google policy.

Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority.

Responsibilities

• Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements.
• Utilize high-level performance and power models to guide architectural decisions and conduct detailed trade-off analyses to optimize for system-level goals.
• Create and maintain detailed architectural specification documents that guide micro-architecture and design teams throughout the project lifecycle.
• Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements.
• Drive the technical evaluation, selection, and integration strategy for key third-party IP cores and technologies. Research emerging technologies and industry trends to influence and contribute to the long-term silicon and system architecture roadmap.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering or a related field and 4 years of experience in the job offered or in a Silicon Architect-related occupation.
• Position requires the following: 4 years of experience in Microarchitecture design such as pipelines, caches, TLBs, execution systems, memory; 4 years of experience in System-level optimization or SoC-level optimization such as performance, power, reliability, cost; 4 years of experience in IP integration or Silicon IP integration for System-on-Chip (SoC) designs; 4 years of experience in RTL code analysis such as Verilog or VHDL; 4 years of experience in Technical leadership such as project planning and driving decisions with stakeholders; 1 year of experience in Machine Learning (ML) accelerator architecture design