RTL Design Engineer, Digital Signal Processing

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a RTL Design Engineer, you will be the driving factor behind the physical implementation of next-generation TPU technology. You will own the critical path from mathematical model to bit-exact silicon. You will transform complex Digital Signal Processing (DSP) algorithms into high-performance, power-efficient RTL, ensuring that our AI/ML hardware acceleration meets the extreme demands of Google's global infrastructure.

In this role, you will join a high-impact team focused on developing custom silicon solutions for TPUs. Your expertise in front-end design flows will be essential in delivering the hardware that powers Google's advanced AI models and cloud services.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead the RTL design and implementation of high-speed blocks. Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
  
• Transform high-level architectural specifications and communication theory models into efficient, bit-exact SystemVerilog/Verilog implementations.
  
• Perform fixed-point analysis and micro-architectural trade-offs to optimize for area, power, and performance.
  
• Drive the front-end design flow, including synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalency Checking (LEC) to ensure robust, sign-off quality designs.
  
• Collaborate closely with verification teams to develop bit-exact C++/SystemC models and UVM environments for comprehensive RTL verification.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 10 years of experience in design for Digital Signal Processing (DSP) or high-speed digital logic.
• Experience in Verilog/SystemVerilog or VHDL.
• Experience with MATLAB, Python, or C++ for algorithmic modeling and verification.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience taking complex DSP designs through the full front-end flow: Synthesis (Design Compiler/Genus), STA (PrimeTime/Tempus), and CDC/LEC (Spyglass/Conformal).
• Experience implementing digital blocks for Communication Systems or PHY (e.g., filters, interpolators, or equalizers).
• Experience with advanced FinFET process nodes (e.g., 5nm, 3nm) and achieving timing closure at GHz frequencies.
• Understanding of low-power design techniques and dynamic power optimization.