Staff Engineer, CPU Architectural Modeling & ISA Simulation

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU architectural modeling and ISA simulation strategy, shaping how our out-of-order RISC-V CPUs are modeled, validated, and checked against architectural intent, privileged architecture requirements, and system-visible correctness across the pre-silicon verification stack.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are 

• You bring 8+ years in CPU architectural modeling, ISA simulation, reference model development, CPU architectural verification, or closely related CPU validation work.
• You have strong experience building, extending, or validating functional models and simulators for CPU pipelines, ISA behavior, privileged architecture, and exception handling.
• You understand RISC-V ISA behavior, memory ordering, trap and interrupt flows, and high-performance out-of-order CPU microarchitecture in depth.
• You are comfortable debugging architectural mismatches using RTL, waveforms, logs, traces, reference models, and complex test scenarios across simulation and emulation.
• You communicate clearly across architecture, design, DV, emulation, compiler, and post-silicon teams.

 

What We Need 

• Lead development and refinement of architectural and functional models for high-performance out-of-order RISC-V CPUs, with emphasis on ISA correctness and system-visible behavior.
• Build, extend, and maintain ISA simulation and reference-model infrastructure used to validate CPU features, privileged architecture flows, and emerging RISC-V extensions.
• Define model-based validation strategies, including checker integration, differential testing, scoreboarding, and architectural coverage methods across simulation and emulation environments.
• Debug architectural failures by isolating RTL versus model mismatches, root-causing correctness issues, and driving closure with CPU architecture, design, and verification teams.
• Develop and debug functional models of RISC-V extensions and CPU-adjacent components relevant to architectural correctness, integration, and performance-aware validation.
• Improve core, cluster, and chip-level infrastructure to better support model bring-up, debug scalability, and shared validation workflows across CPU programs.

 

What You Will Learn 

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for scaling architectural models, ISA simulation, and checker infrastructure across complex CPU programs.
• Ways to connect reference models, simulation, emulation, and post-silicon debug into a shared architectural validation workflow.
• How open hardware and software fit into Tenstorrent’s broader compute roadmap.

 

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.