Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration
As a part of the Google Silicon Platforms team, you will work on verification of the backbone of Google’s SOC offerings. You collaborate with hardware architects and design engineers for functional and performance verification of infrastructure IP, interconnects, caches, memory management, and system services. You will also work on developing high performance VIPs for protocols supported by our SOCs and closely collaborate on the deployment of the verification stack across a heterogeneous set of IPs.
Our approach to building systems is based on scalability. Your work will include building and verifying a generalized class of system topology abstractions and developing the associated methodologies and tools needed to solve the problem.
As an
ASIC Design Verification Engineer, you will be part of a research and development team, and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about
benefits at Google.
Responsibilities
- Plan and execute the verification of next-generation configurable infrastructure IPs, interconnects, and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems.
- Close coverage measures to identify verification holes and show progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience verifying digital logic at RTL level using SystemVerilog or C/C++.
- Experience creating and using verification components and environments in standard verification methodology (e.g., UVM, SVA, CRV, PSS or LPDV).
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience with scripting languages and software development frameworks.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
- 7 years of experience with building verification methodologies that span simulation, formal, emulation, and FPGA prototyping.
- Experience with interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
- Experience with performance verification of SOCs, pre-silicon analysis and post-silicon correlation.
- Experience with architectural background in one or more of the following: caches hierarchies, coherency, memory consistency models, DDR/LPDDR, PCIe, packet processors, security, clock, and power controllers.