WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.
THE PERSON:
The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise in both performance and power optimization, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.
KEY RESPONSIBILITIES:
- RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets, with strong emphasis on power-efficient design and timing requirements.
- Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, low-power intent definition (UPF/CPF), timing analysis, verification, physical design integration, and post-silicon validation.
- Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing and power closure.
- Low-Power Design & Analysis: Implement advanced low-power techniques such as clock gating, power gating, multi-voltage domains, dynamic voltage and frequency scaling (DVFS), and retention strategies; analyze and optimize dynamic and leakage power across design stages.
- Power Intent & Verification: Define and validate power intent using UPF/CPF; ensure correct implementation of power domains, isolation, level shifters, and retention cells; collaborate with verification teams on power-aware simulations and checks.
- Design Quality & Verification: Partner with verification teams to ensure comprehensive functional and power-aware coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality and low-power signoff reviews.
- Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, including power analysis flows, design quality checks, and reporting, improving efficiency across the design cycle.
- Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges related to performance and power, delivering high-quality silicon on schedule.
REQUIRED QUALIFICATIONS:
- Proven track record with 2+ production ASIC tape-outs in senior design roles
- Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
- Hands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-out
- Strong experience in low-power design methodologies and implementation (clock gating, power gating, multi-voltage design)
- Experience with power intent formats such as UPF or CPF and power-aware verification flows
- Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
- Experience integrating complex IP blocks into SOC designs with multiple power domains
- Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
PREFERRED QUALIFICATIONS:
- Knowledge of ARM architecture and AMBA protocol specifications
- Familiarity with PCIe or CXL transaction layer protocols
- Experience with advanced power analysis tools (PrimePower, Voltus, RedHawk or equivalent)
- Experience in power integrity analysis including IR drop and electromigration (EM)
- Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
- Exposure to formal verification tools for equivalence checking and property verification
- Familiarity with AI-assisted design tools and modern EDA technologies
- Experience mentoring junior engineers and leading design teams
- Strong technical writing skills for design specifications and documentation
- Excellent communication and collaboration skills in cross-functional environments
KEY SKILLS & COMPETENCIES:
Verilog RTL Design • SystemVerilog • Static Timing Analysis (STA) • Synthesis & Optimization • Timing Constraints (SDC) • Clock Domain Crossing (CDC) • Lint & Design Quality • SOC Integration • AMBA Protocols (AXI/AHB/APB) • Design for Test (DFT) • Low Power Design • Scripting (Python/Perl/Tcl) • EDA Tools (Synopsys/Cadence) • Technical Leadership • Problem Solving
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in Electrical or Computer Engineering, or Computer Science.
This role is not eligible for visa sponsorship.
#LI-RW
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.
THE PERSON:
The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise in both performance and power optimization, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.
KEY RESPONSIBILITIES:
- RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets, with strong emphasis on power-efficient design and timing requirements.
- Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, low-power intent definition (UPF/CPF), timing analysis, verification, physical design integration, and post-silicon validation.
- Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing and power closure.
- Low-Power Design & Analysis: Implement advanced low-power techniques such as clock gating, power gating, multi-voltage domains, dynamic voltage and frequency scaling (DVFS), and retention strategies; analyze and optimize dynamic and leakage power across design stages.
- Power Intent & Verification: Define and validate power intent using UPF/CPF; ensure correct implementation of power domains, isolation, level shifters, and retention cells; collaborate with verification teams on power-aware simulations and checks.
- Design Quality & Verification: Partner with verification teams to ensure comprehensive functional and power-aware coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality and low-power signoff reviews.
- Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, including power analysis flows, design quality checks, and reporting, improving efficiency across the design cycle.
- Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges related to performance and power, delivering high-quality silicon on schedule.
REQUIRED QUALIFICATIONS:
- Proven track record with 2+ production ASIC tape-outs in senior design roles
- Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
- Hands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-out
- Strong experience in low-power design methodologies and implementation (clock gating, power gating, multi-voltage design)
- Experience with power intent formats such as UPF or CPF and power-aware verification flows
- Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
- Experience integrating complex IP blocks into SOC designs with multiple power domains
- Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
PREFERRED QUALIFICATIONS:
- Knowledge of ARM architecture and AMBA protocol specifications
- Familiarity with PCIe or CXL transaction layer protocols
- Experience with advanced power analysis tools (PrimePower, Voltus, RedHawk or equivalent)
- Experience in power integrity analysis including IR drop and electromigration (EM)
- Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
- Exposure to formal verification tools for equivalence checking and property verification
- Familiarity with AI-assisted design tools and modern EDA technologies
- Experience mentoring junior engineers and leading design teams
- Strong technical writing skills for design specifications and documentation
- Excellent communication and collaboration skills in cross-functional environments
KEY SKILLS & COMPETENCIES:
Verilog RTL Design • SystemVerilog • Static Timing Analysis (STA) • Synthesis & Optimization • Timing Constraints (SDC) • Clock Domain Crossing (CDC) • Lint & Design Quality • SOC Integration • AMBA Protocols (AXI/AHB/APB) • Design for Test (DFT) • Low Power Design • Scripting (Python/Perl/Tcl) • EDA Tools (Synopsys/Cadence) • Technical Leadership • Problem Solving
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in Electrical or Computer Engineering, or Computer Science.
This role is not eligible for visa sponsorship.
#LI-RW
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.