WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
The Role
We are seeking a lead Power Architect to take subsystem / workstream ownership across power management algorithms, power delivery (PDN), and power integrity (PI), and to drive closure of cross‑functional power readiness items through program milestones. This role will operate as a technical leader and execution driver, translating platform and use‑case needs into actionable power architecture requirements, ensuring robust PI/PDN readiness, and partnering closely with power modeling to keep assumptions, targets, and projections aligned.
Key Responsibilities
1) Power Management Algorithms & Feature Architecture
Own the definition/refinement of power management feature sets and algorithmic behaviors (low power modes, performance states, transitions/state tables) in partnership with PMFW/FW/BIOS and platform stakeholders.
Drive clear articulation of use cases → power behavior requirements, including guardbands/constraints that impact targets and bounding box decisions.
Lead technical reviews for power management architecture readiness and track feature closures across teams (arch ↔ FW/BIOS ↔ validation).
2) PDN Ownership – Rail Planning, Current/Power Requirements, and Tradeoffs
Own rail-level power/current requirement definition across representative operating points and key workloads; provide actionable requirements to platform/package and drive rail tradeoffs and consolidation proposals with senior power architects.
Produce and maintain program collateral: rail maps, power/current profiles, and “what changes what” analysis for platform readiness discussions.
3) PI Leadership – Noise / Droop / IR / State-Transition Robustness
Lead PI execution for assigned critical rails and interfaces, including mission mode and state transitions, ensuring modeling readiness, closure of blockers, and a clear mitigation path (decaps, on‑die regulation, input rail choices, etc.).
Drive the PI handshake across stakeholders (SIPI/packaging/platform/PHY teams), ensuring requirements and inputs are in place and outcomes are tracked to closure.
4) Bounding Box / Targets / Program Readiness
Drive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).
Own a structured “open items” closure mechanism for power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.
5) Tight Partnership with Power Modeling
Partner closely with the power modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.
Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.
Preferred Experience
Strong understanding of SoC power architecture fundamentals: rails, low power modes, performance states, and power targets/use cases.
Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
Demonstrated ability to lead complex cross‑functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform).
Experience leading PI/PDN analysis closure across rails/interfaces and translating results into architecture/platform requirements.
Familiarity collaborating with pre‑silicon power modeling teams and aligning architecture assumptions/targets with projections.
Experience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).
Academic Credential
Location: Austin, TX
This role is not eligible for visa sponsorship.
#LI-BW2
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
The Role
We are seeking a lead Power Architect to take subsystem / workstream ownership across power management algorithms, power delivery (PDN), and power integrity (PI), and to drive closure of cross‑functional power readiness items through program milestones. This role will operate as a technical leader and execution driver, translating platform and use‑case needs into actionable power architecture requirements, ensuring robust PI/PDN readiness, and partnering closely with power modeling to keep assumptions, targets, and projections aligned.
Key Responsibilities
1) Power Management Algorithms & Feature Architecture
Own the definition/refinement of power management feature sets and algorithmic behaviors (low power modes, performance states, transitions/state tables) in partnership with PMFW/FW/BIOS and platform stakeholders.
Drive clear articulation of use cases → power behavior requirements, including guardbands/constraints that impact targets and bounding box decisions.
Lead technical reviews for power management architecture readiness and track feature closures across teams (arch ↔ FW/BIOS ↔ validation).
2) PDN Ownership – Rail Planning, Current/Power Requirements, and Tradeoffs
Own rail-level power/current requirement definition across representative operating points and key workloads; provide actionable requirements to platform/package and drive rail tradeoffs and consolidation proposals with senior power architects.
Produce and maintain program collateral: rail maps, power/current profiles, and “what changes what” analysis for platform readiness discussions.
3) PI Leadership – Noise / Droop / IR / State-Transition Robustness
Lead PI execution for assigned critical rails and interfaces, including mission mode and state transitions, ensuring modeling readiness, closure of blockers, and a clear mitigation path (decaps, on‑die regulation, input rail choices, etc.).
Drive the PI handshake across stakeholders (SIPI/packaging/platform/PHY teams), ensuring requirements and inputs are in place and outcomes are tracked to closure.
4) Bounding Box / Targets / Program Readiness
Drive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).
Own a structured “open items” closure mechanism for power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.
5) Tight Partnership with Power Modeling
Partner closely with the power modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.
Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.
Preferred Experience
Strong understanding of SoC power architecture fundamentals: rails, low power modes, performance states, and power targets/use cases.
Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
Demonstrated ability to lead complex cross‑functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform).
Experience leading PI/PDN analysis closure across rails/interfaces and translating results into architecture/platform requirements.
Familiarity collaborating with pre‑silicon power modeling teams and aligning architecture assumptions/targets with projections.
Experience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).
Academic Credential
Location: Austin, TX
This role is not eligible for visa sponsorship.
#LI-BW2
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.