About Etched

Etched is building the world’s first AI inference system purpose-built for transformers — delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is building dedicated optical I/O expertise to support the next generation of our inference systems. We are hiring a Founding Optical I/O Engineer to be our first dedicated optics hire and to own optical interconnect from architecture through bring-up.

This is a hands-on senior IC role with a clear path to growing a team behind you. The right candidate combines deep technical credibility in silicon photonics, optical packaging, or high-speed optical signaling with the judgment to drive a complex technology from concept to working silicon.

Key Responsibilities

• Define and own Etched’s optical I/O architecture from photonic engine design through system integration

• Specify optical interconnect requirements (bandwidth density, reach, latency, power, packaging) derived from system-level constraints

• Design and bring up the photonic integrated circuits, light sources, and optical packaging that make up Etched’s optical I/O, working with foundry and assembly partners as needed

• Drive co-design between optical I/O and the rest of the chip and system: SerDes, package, substrate, and thermal

• Own the engineering relationships with optical assembly partners

• Recruit and grow the team that will execute against the roadmap

• Partner closely with ASIC, platform, and supercomputing teams to ensure optical I/O integrates cleanly with system architecture

• Represent Etched’s optical I/O work externally

Must-Have Skills and Experience

• 8+ years of experience in silicon photonics, optical I/O, co-packaged or near-packaged optics, or high-speed optical signaling

• Deep expertise in at least one of the following clusters:

◦ Silicon photonics device and PIC design (modulators, photodetectors, waveguides, packaging-aware design)

◦ Optical packaging and assembly (fiber attach, laser integration, thermal management, hermetic and non-hermetic approaches)

◦ High-speed optical signaling and DSP (PAM4, coherent, SerDes-to-optical integration, link budget analysis)

• Demonstrated experience shipping or bringing up a real optical I/O or transceiver product, ideally at 100G/lane or higher

• Strong understanding of the electrical-optical boundary: how SerDes, driver, TIA, and PIC interact at the system level

• Comfortable making architectural decisions under uncertainty - trading off bandwidth, power, reach, cost, and manufacturability, and sequencing a roadmap accordingly

Nice to Have

• Direct experience with NPO, CPO, or optical chiplet integration

Background in one or more of: silicon photonics, optical transceiver, or optical I/O organization

• Hands-on packaging and process integration experience with 2.5D/3D advanced packaging (CoWoS or equivalent)

• Publication track record at OFC, ECOC, ISSCC, or Hot Chips

Benefits

• Medical, dental, and vision packages with generous premium coverage

• $500 per month credit for waiving medical benefits

• Housing subsidy of $2k per month for those living within walking distance of the office

• Relocation support for those moving to San Jose (Santana Row)

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.