FPGA Power Management Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

We are seeking an experienced FPGA Power Management Engineer to join AMD’s FPGA Power Architecture team, helping bring adaptive, workload‑aware power management capabilities into next‑generation FPGA platforms.

In this role, you will architect, implement, and validate closed‑loop DVFS (Dynamic Voltage and Frequency Scaling) and adaptive voltage scaling systems, bridging architecture, RTL, firmware, and lab validation. This is a hands‑on position with real impact on production silicon, focused on improving performance‑per‑watt across demanding data center and defense use cases.

 

As an early hire in this effort, you will play a key role in shaping how power intelligence is designed, validated, and deployed across AMD FPGA platforms.

 

THE PERSON: 

The ideal candidate brings a strong background in silicon or FPGA power management, with demonstrated experience translating architectural power goals into working, measurable systems.

 

You are comfortable working across abstraction levels—from power‑performance modeling and architecture simulation to RTL, firmware integration, and lab bring‑up—and enjoy collaborating with silicon, firmware, and validation teams to ship robust, scalable solutions.

 

This role is best suited for someone who has done power optimization in real hardware, understands the trade‑offs involved, and is motivated to push performance‑per‑watt boundaries in complex systems.

 

KEY RESPONSIBILITIES: 

• Design and implement closed-loop DVFS control subsystems on FPGA to deliver power savings while preserving timing margins across workloads.
• Develop power–performance optimization models (e.g., Energy-Delay Product) to determine optimal voltage–frequency operating points for compute-intensive kernels.
• Drive timing closure for DVFS-enabled logic islands, including timing-constrained synthesis and place-and-route.
• Lead silicon bring-up and power characterization, using lab instrumentation to measure voltage droop, power-grid transients, and power profiles.
• Partner with silicon design, firmware, and validation teams to deliver scalable, production-ready power management solutions

 

PREFERRED EXPERIENCE: 

• Demonstrated experience optimizing power consumption and performance using techniques such as DVFS and AVS.
• Strong background in power‑performance modeling using metrics such as EDP, PPW, or MIPS/W.
• Hands‑on RTL design experience in Verilog / SystemVerilog, including AXI4‑Lite interfaces.
• Experience with modern FPGA platforms, including Xilinx UltraScale+ or Versal; familiarity with Intel Agilex is a plus.
• Experience with hardware/firmware co‑design, spanning bare‑metal or RTOS‑based systems.
• Solid understanding of VLSI fundamentals, timing closure, CDC, and metastability.
• Practical experience with lab bring‑up, power integrity, telemetry, and power control interfaces (e.g., PMBus, SVI3).
• Familiarity with statistical power analysis techniques is a plus.
• Strong communication skills and ability to collaborate across global teams. 

 

ACADEMIC CREDENTIALS: 

• Ph.D. or M.S. in Electrical Engineering preferred

 

LOCATION: 

• San Jose, CA, flexibility may be considered for exceptional candidates.

 

This role is not eligible for visa sponsorship

 

#LI-DR2

#LI-Hybrid

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

We are seeking an experienced FPGA Power Management Engineer to join AMD’s FPGA Power Architecture team, helping bring adaptive, workload‑aware power management capabilities into next‑generation FPGA platforms.

In this role, you will architect, implement, and validate closed‑loop DVFS (Dynamic Voltage and Frequency Scaling) and adaptive voltage scaling systems, bridging architecture, RTL, firmware, and lab validation. This is a hands‑on position with real impact on production silicon, focused on improving performance‑per‑watt across demanding data center and defense use cases.

 

As an early hire in this effort, you will play a key role in shaping how power intelligence is designed, validated, and deployed across AMD FPGA platforms.

 

THE PERSON: 

The ideal candidate brings a strong background in silicon or FPGA power management, with demonstrated experience translating architectural power goals into working, measurable systems.

 

You are comfortable working across abstraction levels—from power‑performance modeling and architecture simulation to RTL, firmware integration, and lab bring‑up—and enjoy collaborating with silicon, firmware, and validation teams to ship robust, scalable solutions.

 

This role is best suited for someone who has done power optimization in real hardware, understands the trade‑offs involved, and is motivated to push performance‑per‑watt boundaries in complex systems.

 

KEY RESPONSIBILITIES: 

• Design and implement closed-loop DVFS control subsystems on FPGA to deliver power savings while preserving timing margins across workloads.
• Develop power–performance optimization models (e.g., Energy-Delay Product) to determine optimal voltage–frequency operating points for compute-intensive kernels.
• Drive timing closure for DVFS-enabled logic islands, including timing-constrained synthesis and place-and-route.
• Lead silicon bring-up and power characterization, using lab instrumentation to measure voltage droop, power-grid transients, and power profiles.
• Partner with silicon design, firmware, and validation teams to deliver scalable, production-ready power management solutions

 

PREFERRED EXPERIENCE: 

• Demonstrated experience optimizing power consumption and performance using techniques such as DVFS and AVS.
• Strong background in power‑performance modeling using metrics such as EDP, PPW, or MIPS/W.
• Hands‑on RTL design experience in Verilog / SystemVerilog, including AXI4‑Lite interfaces.
• Experience with modern FPGA platforms, including Xilinx UltraScale+ or Versal; familiarity with Intel Agilex is a plus.
• Experience with hardware/firmware co‑design, spanning bare‑metal or RTOS‑based systems.
• Solid understanding of VLSI fundamentals, timing closure, CDC, and metastability.
• Practical experience with lab bring‑up, power integrity, telemetry, and power control interfaces (e.g., PMBus, SVI3).
• Familiarity with statistical power analysis techniques is a plus.
• Strong communication skills and ability to collaborate across global teams. 

 

ACADEMIC CREDENTIALS: 

• Ph.D. or M.S. in Electrical Engineering preferred

 

LOCATION: 

• San Jose, CA, flexibility may be considered for exceptional candidates.

 

This role is not eligible for visa sponsorship

 

#LI-DR2

#LI-Hybrid

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.