Principal, System HSIO Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

The High‑Speed IO (HSIO) validation engineer is responsible for driving end‑to‑end validation strategy and execution for high‑speed interfaces across CPU and GPU based platforms, spanning data center servers and AI systems. In this highly visible role, you will partner closely with PHY design, SI/PI, and platform teams to validate and debug high‑speed IO subsystems, ensuring robust silicon and system readiness for industry-leading products.

 

WHAT YOU WILL BE DOING

• Own validation strategy, planning, and execution for high‑speed IO interfaces (e.g., PCIe Gen6/Gen7, UALink, XGMI) across multiple platforms.
• Define and execute comprehensive validation plans covering pre‑silicon correlation, post‑silicon bring-up, compliance, margining, and debug methodologies.
• Collaborate cross-functionally with design, architecture, board, firmware, and test teams to ensure coverage completeness and accelerate issue resolution.
• Develop and deploy automated validation infrastructure, lab setups, and data analysis workflows for high‑speed interface characterization.
• Perform deep root-cause analysis for SI/PI issues, protocol failures, and system-level interoperability challenges, working with internal teams and external partners.
• Track validation progress, communicate status and key risks, and ensure quality deliverables aligned with program milestones.

 

WHO WE ARE LOOKING FOR

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field, with 8+ years of experience in high-speed IO or silicon/system validation.
• Strong technical expertise in high-speed serial interfaces (e.g., PCIe Gen5/Gen6, CXL, Ethernet) and associated validation and debug tools (e.g., oscilloscopes, BERTs, protocol analyzers).
• Solid understanding of Tx/Rx equalization techniques (CTLE, DFE, de-emphasis), CDR architectures, and link-level behavior.
• Proven experience driving complex validation efforts across silicon and system bring-up environments.
• Hands-on experience with lab bring-up, test automation (e.g., Python, C/C++), and data analysis for SI/PI and functional validation.
• Deep understanding of signal integrity, power integrity, and system-level debug methodologies.
• Ability to operate effectively in a fast-paced, cross-functional environment and drive issues to closure.

 

EDUCATION:

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field, with 8+ years of experience in high-speed IO or silicon/system validation.

 

Strong commitment to quality, innovation, and continuous improvement.

 

This role is not eligible for visa sponsorship.

 

Location:

Santa Clara, CA

 

#LI-LM1

#LI-HYBRID 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE:

The High‑Speed IO (HSIO) validation engineer is responsible for driving end‑to‑end validation strategy and execution for high‑speed interfaces across CPU and GPU based platforms, spanning data center servers and AI systems. In this highly visible role, you will partner closely with PHY design, SI/PI, and platform teams to validate and debug high‑speed IO subsystems, ensuring robust silicon and system readiness for industry-leading products.

 

WHAT YOU WILL BE DOING

• Own validation strategy, planning, and execution for high‑speed IO interfaces (e.g., PCIe Gen6/Gen7, UALink, XGMI) across multiple platforms.
• Define and execute comprehensive validation plans covering pre‑silicon correlation, post‑silicon bring-up, compliance, margining, and debug methodologies.
• Collaborate cross-functionally with design, architecture, board, firmware, and test teams to ensure coverage completeness and accelerate issue resolution.
• Develop and deploy automated validation infrastructure, lab setups, and data analysis workflows for high‑speed interface characterization.
• Perform deep root-cause analysis for SI/PI issues, protocol failures, and system-level interoperability challenges, working with internal teams and external partners.
• Track validation progress, communicate status and key risks, and ensure quality deliverables aligned with program milestones.

 

WHO WE ARE LOOKING FOR

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field, with 8+ years of experience in high-speed IO or silicon/system validation.
• Strong technical expertise in high-speed serial interfaces (e.g., PCIe Gen5/Gen6, CXL, Ethernet) and associated validation and debug tools (e.g., oscilloscopes, BERTs, protocol analyzers).
• Solid understanding of Tx/Rx equalization techniques (CTLE, DFE, de-emphasis), CDR architectures, and link-level behavior.
• Proven experience driving complex validation efforts across silicon and system bring-up environments.
• Hands-on experience with lab bring-up, test automation (e.g., Python, C/C++), and data analysis for SI/PI and functional validation.
• Deep understanding of signal integrity, power integrity, and system-level debug methodologies.
• Ability to operate effectively in a fast-paced, cross-functional environment and drive issues to closure.

 

EDUCATION:

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field, with 8+ years of experience in high-speed IO or silicon/system validation.

 

Strong commitment to quality, innovation, and continuous improvement.

 

This role is not eligible for visa sponsorship.

 

Location:

Santa Clara, CA

 

#LI-LM1

#LI-HYBRID 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.