SMTS Physical Design Engineer

Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed interface chip program — from synthesis netlist through GDSII tape-out. This is a full-flow PD role on a small, senior team spanning analog design, layout, silicon characterization, digital design, and verification — united around the goal of carrying high-speed interface innovations from architecture to tape-out.

You will be the primary PD voice, working closely with the Chip Lead on timing and constraints, with the analog team on mixed-signal floorplanning considerations, and with the verification team on DFT and scan implementation. The program includes contractor support that will grow as the program scales, but the expectation is that you can drive implementation decisions independently, leverage available resources effectively, and know when to engage the broader team.

The ideal candidate brings not just technical depth but creative problem-solving ability — the capacity to find non-obvious paths to closure when standard approaches don't apply cleanly to a mixed-signal PHY environment. This is a foundational hire for a growing program, and strong execution early is expected to lead to follow-on projects of increasing scope, team size, and PD complexity.

Responsibilities

• Floorplanning: Define and implement full chip floorplans in close collaboration with the analog design team — including custom analog block placement, analog/digital partitioning, I/O ring architecture, power domain definition, and block-level area allocation.

• Power Planning: Design and implement the chip power distribution network (PDN); coordinate with the analog team on analog supply isolation, guard ring placement, and substrate noise considerations.

• Place & Route: Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and optimized database across all required corners and modes.

• Timing Closure: Own static timing analysis (Cadence Tempus) across all PVT corners and modes; identify and resolve timing violations through ECO, placement, and routing optimization; coordinate with the Chip Lead on constraint refinement.

• Power Integrity: Perform IR drop and electromigration analysis (Cadence Voltus or equivalent); identify and resolve PDN weaknesses.

• Physical Verification Sign-off: Execute and close DRC, LVS, and ERC to foundry-clean status using Mentor Calibre; manage waiver process for any non-cleanable violations.

• DFT Integration: Implement scan chain insertion and work with the Chip Lead on ATPG pattern generation and test coverage targets.

• Foundry Coordination: Interface with foundry on PDK questions, fill rule implementation, and tape-out submission requirements.

• Documentation: Maintain PD methodology documentation, floorplan rationale records, and ECO history to support program continuity and follow-on chip development.

Basic Qualifications

• BS, MS, or PhD in Electrical Engineering or related field

• 8–15 years of physical design experience with at least one complete front-to-back tape-out as the primary or lead PD engineer

• Hands-on proficiency with Cadence Innovus for place-and-route — comfortable navigating complex placement constraints, congestion-driven routing, and post-route optimization without step-by-step guidance

• Hands-on proficiency with Cadence Tempus for static timing analysis including MMMC setup, OCV/AOCV analysis, and ECO-driven timing closure

• Hands-on proficiency with Mentor Calibre for DRC, LVS, and ERC sign-off

• Experience placing and integrating hard macros (analog PHY blocks, memory compilers, I/O cells) within a constrained mixed-signal floorplan

• Demonstrated ability to take broad ownership and drive to closure — comfortable leading implementation decisions, working across disciplines, and managing priorities without a large supporting PD organization

• Strong debugging and root-cause analysis skills — the ability to look at a failing DRC deck, a congested routing region, or a timing path that doesn't respond to standard approaches and find a path forward

• Ability to communicate clearly with non-PD engineers — Chip Lead, analog designers, and DV engineers — about physical implementation constraints and their design implications

Preferred Qualifications

• Experience with mixed-signal or analog-adjacent chip physical design — including analog supply domain implementation, substrate isolation techniques, and analog/digital floor separation

• Familiarity with high-speed I/O pad ring design for differential full-duplex interfaces

• Experience with power domain implementation using UPF/CPF for multi-voltage PHY designs

• Proficiency with Cadence Voltus or Apache Redhawk for power integrity analysis

• Familiarity with Synopsys IC Compiler 2 (ICC2) as an alternative P&R environment

• Experience with signoff ECO flows — functional and metal-only ECOs post-tape-out

• Prior experience carrying primary PD responsibility on a chip or significant subsystem — candidates who have navigated the full implementation flow in a lead capacity and found it energizing are strongly preferred