Signal and Power Integrity Engineer

As a Chip Package Signal Integrity/Power Integrity (SI/PI) Engineer, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level. Within a concurrent engineering environment, you will be the main part of a larger team with system architects, ASIC engineers, and other SI/PI engineers. You will work with multi cross-functional teams including chip design team, board design team, system design team as well as vendors. You will drive chip packaging signal and power implementations to meet chip, package and system electrical requirements.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Drive SI/PI analysis and optimization for HPC based on 2.5D/3D technology, influencing product definition, chip floorplan, power tree structures, and netlists.
• Lead the development of next-generation memory interfaces and evaluate high-speed interface IP, considering Input/Output Physical Layer (IO PHY), physical design, and SI/PI requirements.
• Manage post-silicon validation and qualification of high-speed interfaces for New Product Introduction (NPI), ensuring performance meets production standards.
• Partner with chip/system design teams and external vendors to define SI/PI design goals, set chip boundaries, and balance SI/PI and DFM tradeoffs for production closure.
• Develop innovative methodologies to enhance simulation accuracy and productivity while providing critical feedback on chip floorplans to optimize routability and signal integrity.

Minimum qualifications:

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
• 8 years of experience in SI/PI design for chip/package or system PCB.
• Experience in industry SI/PI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience with signal and power integrity with various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe, etc.).
• Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
• Experience in co-design with chip top design, physical design, STA, package, system and validation teams.
• Familiarity with the post SI test environment on memory or high speed serdes.
• Excellent programming and data analysis skills with MATLAB, Python, C++, etc. to establish automation flows and data processing.