FPGA Prototyping and Emulation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

• Create FPGA prototyping builds to validate the IP/SoC functionality
• Collaborate with design, verification and validation teams  to debug issues found during pre-si validation and also support post-silicon validation
• Maintain and improve current hardware prototyping environment to speed up the runtime performance and improve the debug facility 
• Provide technical support to other teams 

 

PREFERRED EXPERIENCE: 

• Strong experience in FPGA prototyping
• Partition large SoC RTL for multi‑FPGA platforms.
• Perform synthesis, place‑and‑route, timing closure, and resource optimization for FPGA builds.
• Develop and maintain FPGA build infrastructure including scripts, flows, and makefiles.
• Integrate custom transactors, high‑speed interfaces, and debug instrumentation.
• Validate system functionality by running architectural tests, diagnostics, directed tests, and firmware.
• Drive debug of functional, timing, or tool‑related issues across FPGA, RTL, and test environments.
• Work across teams (RTL, DV, Emulation, Firmware, Silicon Bring‑up) to root‑cause and resolve issues efficiently.
• Strong RTL design background using SystemVerilog/Verilog.
  
• Hands‑on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms.
  
• Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes‑based links, etc.
  
• Strong debug skills across RTL, simulation, FPGA, and system setups.
  
• Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.
  
• Experience integrating C/C++ or embedded firmware into prototyping flows is a plus.
  
• Familiarity with emulation acceleration, hybrid simulation, or co‑modeling. 

 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

 

LOCATION : San Jose, CA

 

This role is not eligible for visa sponsorship.

 

 

#LI-CJ3

#LI-Hybrid

 

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

• Create FPGA prototyping builds to validate the IP/SoC functionality
• Collaborate with design, verification and validation teams  to debug issues found during pre-si validation and also support post-silicon validation
• Maintain and improve current hardware prototyping environment to speed up the runtime performance and improve the debug facility 
• Provide technical support to other teams 

 

PREFERRED EXPERIENCE: 

• Strong experience in FPGA prototyping
• Partition large SoC RTL for multi‑FPGA platforms.
• Perform synthesis, place‑and‑route, timing closure, and resource optimization for FPGA builds.
• Develop and maintain FPGA build infrastructure including scripts, flows, and makefiles.
• Integrate custom transactors, high‑speed interfaces, and debug instrumentation.
• Validate system functionality by running architectural tests, diagnostics, directed tests, and firmware.
• Drive debug of functional, timing, or tool‑related issues across FPGA, RTL, and test environments.
• Work across teams (RTL, DV, Emulation, Firmware, Silicon Bring‑up) to root‑cause and resolve issues efficiently.
• Strong RTL design background using SystemVerilog/Verilog.
  
• Hands‑on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms.
  
• Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes‑based links, etc.
  
• Strong debug skills across RTL, simulation, FPGA, and system setups.
  
• Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.
  
• Experience integrating C/C++ or embedded firmware into prototyping flows is a plus.
  
• Familiarity with emulation acceleration, hybrid simulation, or co‑modeling. 

 

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

 

LOCATION : San Jose, CA

 

This role is not eligible for visa sponsorship.

 

 

#LI-CJ3

#LI-Hybrid

 

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.