Senior Power and Thermal Engineer - Feature Design and Verification 

What you'll be doing:

• Work with design owners across the company to understand chip, module, and datacenter power features and develop in-depth system design plans to meet compliance using AI tools to bridge cross-team assumption gaps and accelerate documentation.

• BringUp and validate compliance features on silicon; apply AI-driven tools to reduce debug cycle time and correlate silicon behavior with simulation at scale.

• Deliver system-level power optimizations spanning across silicon, platform, software, manufacturing, and product systems; create/leverage AI models for power prediction, binning optimization, and Vmin/Fmax characterization across products.

• Lead power feature requirements and schedule from architecture to silicon; build or guide the development of AI agents scoped to your charter, such as thermal-to-SW assumption checkers, binning coherence agents, or state machine verification agents.

• Develop AI-agentic methodologies for power modeling, measurement, and characterization; drive silicon-to-simulation correlation; and create/establish data pipelines and human-in-the-loop review workflows to accelerate codesign.

• Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, ATE engineers, and AI engineering partners to bring industry-defining products to market.

What we need to see:

• BS or MS in EE, CE, CS, Systems Engineering, or equivalent experience.

• 6+ years in the area of silicon and product power and power management, with expertise in transistor/device physics, power modeling, measurement, and active power management.

• Experience with system-level features, product binning methods, optimization techniques, and tools for data analysis and statistics.

• Familiarity with AI/ML-assisted workflows for power characterization, yield analysis, silicon debug, or log correlation, including comfort using Python, LLMs, or data science tooling alongside core EDA flows.

• Hands-on post-silicon bring-up and validation experience; frequency and power characterization background strongly preferred.

• Experience working with offshore teams is required; excellent problem-solving, partnership, and interpersonal skills are required.

• Exposure to CPU/GPU/SoC architecture and HW-SW co-design is a plus.

Ways to stand out from the crowd:

• You are a codesign engineer who has learned to build with AI to understand power design and cross-design well enough to specify what an agent must know, evaluate its output, and create closed-loop workflows.

• Hands-on experience building or piloting AI agents, copilots, or automation tools within a power, thermal, or silicon validation workflow, not just using AI tools, but shaping them for domain-specific problems.

• Track record of using LLMs or ML models to catch the class of bugs that live in assumptions between teams, thermal-to-software, power-to-binning, or spec-to-silicon mismatches.

• Familiarity with the full codesign arc (Innovate to Realize) and experience identifying handoff points where agents can assist or automate cross-team contract verification. Publications, open-source contributions, or internal tooling that demonstrates applied AI expertise in an EDA, semiconductor, or hardware validation context.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

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