Virtual Platforms & SoC Modeling Engineer

Meta’s Silicon Engineers are at the forefront of innovation, driving the design and development of silicon that power the future of human connection. Across Infrastructure, Reality Labs, and Research, our teams tackle complex challenges in wearables, data centers, and more. We bring together cross-disciplinary minds to invent, prototype, and deliver products and platforms that connect billions of people worldwide. We're seeking a modeling engineer to develop silicon models, in partnership with architecture, firmware, emulation and other domain experts, which serve as foundational tools for architectural exploration for our next-generation custom silicon solutions.

Responsibilities

• Design and develop high-level models of complex SoC hardware using SystemC TLM, and other simulation frameworks
• Collaborate with silicon architects, digital designers, and verification engineers to design and develop high-fidelity models for first-party and third-party IPs
• Work with architecture teams to understand SoC and IP architecture, enabling Software/Hardware co-design using pre-silicon platforms
• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in hardware model simulation, virtual platform, performance modeling of complex SoCs, or high-fidelity hardware accelerators
• Proficiency in modern C++ and/or C programming languages
• General familiarity with SoC components, including embedded processors, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols
• Experience with SystemC, TLM, or other simulation frameworks Proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation
• Experience in at least one of these areas - embedded processors such as ARM A/M series, RISC-V, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols
• Experience with modern build frameworks and continuous integration systems, such as CMake, Bazel and CI frameworks such as Jenkins, GitLab CI/CD
• Experience with debugging and profiling tools, such as GDB or other debuggers
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc
• Familiarity with power and performance metrics instrumentation in pre-silicon platforms
• Proficiency in Python to automate design flows and generate necessary collateral data
• Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
• Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
• Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies