In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge
TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's
TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on
TPU architecture and its integration within AI/ML-driven systems.
In this role, you will work with vendors to manage deliveries of Application-specific integrated circuit (
ASIC) libraries. You will manage the verification and installation of vendor libraries for live
ASIC projects, ensuring correctness and consistency across releases.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about
benefits at Google.
Responsibilities
- Manage the handoff of library collateral (e.g., Taiwan Semiconductor Manufacturing Company (TSMC) process design kits (PDKs), Synopsys, and other third-party intellectual properties (IPs)) to projects, performing checks to ensure data integrity.
- Drive library validation across views (.lib, .db, .ndm, .lef, .gds) using tools like Siemens Solido Crosscheck (formerly Fractal Crossfire).
- Perform Logic Equivalency Checking (LEC) using tools such as Formality or Conformal.
- Oversee library updates in ASIC projects, applying methodical processes to detect and prevent errors during releases.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with managing vendor engagements and library delivery schedules in an ASIC design environment.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in Logic Equivalency Checking (LEC) (e.g., Formality or Conformal).
- Familiarity with practices for managing ASIC project library updates and releases.
- Proficiency in library validation tools (e.g., Solido Crosscheck) and understanding of foundation library PDKs from foundries (e.g., TSMC).
- Demonstrated ability to compile libraries and debug issues across design views (.lib, .db, .ndm, .lef, .gds).
- Skills with scripting languages such as Tcl or Python to automate workflows and experience creating technology library management and installation flows with integrated validation.