Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will lead and manage a global team of Verification Engineers and independently own Verification closure of various Machine Learning (ML) Accelerators and Multimedia IP designs. This includes verification methodology, infrastructure, test-benches, planning, metrics development and convergence of metrics to deliver high quality ISP Designs.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about
benefits at Google.
Responsibilities
- Plan the verification of complex ML and multimedia hardware at IP and Subsystem level and while supporting full chip level integration by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases, work with design engineers to debug tests to deliver functionally correct design blocks.
- Manage and mentor a global team of design verification engineers, including methodology department, in all aspects of design verification including test plan reviews, coverage analysis, regression/simulation and debug, and schedule planning for quality verification milestones.
- Manage the interface between SoC Design Verification teams and the ML/Multimedia Hardware Design Verification team including required deliverables for all SoC verification milestones.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with verifying digital logic at RTL using SystemVerilog for ASICs.
- Experience leading a team completing the full functional verification and performance validation cycle of subsystems such as Camera ML/Multemedia/ISP, Display, TPU/GPU, processors, or at the SOC level.
- Experience constructing reusable verification components and environments using UVM.
- Experience with object oriented programming.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Camera ISP image processing or other Multimedia IPs such as Display or Video Codec or ML Accelerator verification.
- Experience with System Verilog Assertions (SVA), assertion-based verification, and formal verification.
- Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
- Experience working with RTL design and integration teams on methodologies that improve team productivity and velocity.
- Experience with Low Power Verification and power management flows.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
San Diego, CA, USA; Mountain View, CA, USA.