Chip Package Signal and Power Integrity Engineer

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Chip Package Signal integrity/Power Integrity (SI/PI) Engineer in the chip implementation team, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the package and system level. You will be part of a larger team with system architects, ASIC engineers, and other SI/PI engineers. You will work with cross-functional teams including chip design team, board design team, system design team and vendors. You will drive chip packaging signal and power implementations to meet chip, package and system electrical requirements.

Our computational challenges are so complex and unique we can't purchase off-the-shelf hardware, we make it ourselves. We design and build the hardware, software and networking technologies that power all of Google's services. You design and build the systems that are the heart of the world's most powerful computing infrastructure. You will see systems from concept to high volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Drive chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for HPC based on 2.5D/3D package technology.
• Develop Power integrity methodology for advanced package technology, and Methodology development to enhance accuracy and productivity.
• Evaluate New package technology and development, and High speed Interface IP.
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, define boundaries of chip design and explore SI/PI and DFM trad-eoff for package design closure for production.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with SI/PI design for chip/package or system PCB.
• Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or SI/PI.
• Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
• Knowledge of next-generation memory and chiplet standards, including timing budget, design & sign-off methodologies.
• Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
• Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.
• Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.