Reality Labs is building the hardware that powers Meta's next generation of AR display products. In this role you will own the Display Silicon Integration scope across the team's silicon programs: the work that turns a tested silicon die into a working, shippable display. This is a senior, multi-program, multi-foundry, multi-supplier role. The right candidate is comfortable managing a complex execution surface and driving cross-functional alignment without formal authority over the engineering teams involved.
Responsibilities
- Own end-to-end Display Silicon Integration execution for one or more programs, accountable for the entire lifecycle from post-tapeout silicon delivery through production ramp
- Drive complex silicon-to-display integration, coordinating Meta silicon design, display module engineering, Display systems engineering, and external suppliers to land new silicon revisions into working modules and resolving interface, packaging, and yield issues
- Lead FACA (failure analysis and corrective action) cycles, driving the full technical investigation and closure across foundry, display supplier, and internal teams. This includes making trade-off calls between root-causing, working around, and accepting risk
- Coordinate wafer scale-up across foundries. Manage wafer flow, capacity commitments, contractual obligations, and storage / aging windows
- Partner with adjacent TPMs to hold the Display Silicon Integration slice cleanly across all programs in scope
- Translate technical reality up. Surface integration risks, timeline slippage, and vendor commitment gaps to leadership directly and with evidence
Minimum Qualifications
- 5+ years of TPM experience in semiconductor execution, with at least 3 years in roles that touched silicon-to-display module or product integration (not pure SoC tapeout TPM)
- Demonstrated ownership of multi-foundry programs. You have worked with at least two foundries on real silicon, ideally including both a mature and a leading-edge node
- Direct FACA experience driving failure analysis cycles that crossed foundry, supplier, and internal team boundaries and produced shippable outcomes
- Direct wafer scale-up experience, including wafer flow, capacity, and contractual mechanics with external foundries
- Experience making program-level decisions under incomplete information, including when to escalate risks, defer action, or proceed based on available data Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
- Prior work in AR/VR, mobile, or other power- and area-constrained silicon contexts
- Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
- Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
- Experience with display backplane silicon or other vertically-integrated hardware where the silicon is one component of a larger product
- Experience writing and presenting executive-facing technical narratives