PCIe, CXL and Highspeed IO Validation Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

 

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

PCIe, CXL and Highspeed IO Validation Engineer  

 

 

THE ROLE:

We are looking for a dynamic, energetic, and visionary principal validation engineer to join our growing datacenter CPU post silicon validation team, in particular in the areas of highspeed IO such as PCI Express and Compute Express Link (CXL), multi-socket and inter-die interfaces. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering and validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.  

 

KEY RESPONSIBILITIES:

• Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IO
• Develop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testing
• Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
• Test interactions between various SoC features using validation infrastructure
• Debug and drive root-cause analysis for SoC related issues
• Collaborate with cross-functional teams in developing tools to improve SoC validation and debug
• Work with cross-functional teams to improve post-silicon validation test strategy, methodology, and process

  

PREFERRED EXPERIENCE:  

• Proven hands on experience in soc design or validation of high speed IO interfaces
• Has experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both. 
• Understanding of modern x86 microprocessor architecture and Server platform architecture is highly desired
• Experience developing validation methodologies and infrastructure
• Test plan and workload development experience
• Participated in silicon bring up and debug, support to internal engineering teams
• Able to execute and drive success of programs with multiple projects on the go
• Debug skills at both SoC and system level
• Familiarity with programming / scripting language (C/C++, Python, Perl, ...)
• Working knowledge of Server OSes (Linux, Windows)
• Must be a self-starting team player with excellent communication skills who can work with minimal guidance
• Forward thinker that drives improvement to development process, code architecture and fosters a spirit of innovation and continuous improvement
• Strong verbal and written English communication skills
• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.  
• Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization 
• Extensive knowledge of system architecture, technical debug, and validation strategy 
• Strong analytical/problem-solving skills and pronounced attention to details

  

ACADEMIC CREDENTIALS:  

• BSEE/CSE/CS with 7+ years of experience or
• MSEE/CSE/CS with 5+ years of experience

 

LOCATION:

Austin, TX

Santa Clara, CA

 

 

This role is not eligible for visa sponsorship.

 

#LI-LM1

#LI-HYBRID 

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

PCIe, CXL and Highspeed IO Validation Engineer  

 

 

THE ROLE:

We are looking for a dynamic, energetic, and visionary principal validation engineer to join our growing datacenter CPU post silicon validation team, in particular in the areas of highspeed IO such as PCI Express and Compute Express Link (CXL), multi-socket and inter-die interfaces. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering and validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.  

 

KEY RESPONSIBILITIES:

• Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IO
• Develop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testing
• Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
• Test interactions between various SoC features using validation infrastructure
• Debug and drive root-cause analysis for SoC related issues
• Collaborate with cross-functional teams in developing tools to improve SoC validation and debug
• Work with cross-functional teams to improve post-silicon validation test strategy, methodology, and process

  

PREFERRED EXPERIENCE:  

• Proven hands on experience in soc design or validation of high speed IO interfaces
• Has experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both. 
• Understanding of modern x86 microprocessor architecture and Server platform architecture is highly desired
• Experience developing validation methodologies and infrastructure
• Test plan and workload development experience
• Participated in silicon bring up and debug, support to internal engineering teams
• Able to execute and drive success of programs with multiple projects on the go
• Debug skills at both SoC and system level
• Familiarity with programming / scripting language (C/C++, Python, Perl, ...)
• Working knowledge of Server OSes (Linux, Windows)
• Must be a self-starting team player with excellent communication skills who can work with minimal guidance
• Forward thinker that drives improvement to development process, code architecture and fosters a spirit of innovation and continuous improvement
• Strong verbal and written English communication skills
• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.  
• Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization 
• Extensive knowledge of system architecture, technical debug, and validation strategy 
• Strong analytical/problem-solving skills and pronounced attention to details

  

ACADEMIC CREDENTIALS:  

• BSEE/CSE/CS with 7+ years of experience or
• MSEE/CSE/CS with 5+ years of experience

 

LOCATION:

Austin, TX

Santa Clara, CA

 

 

This role is not eligible for visa sponsorship.

 

#LI-LM1

#LI-HYBRID 

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.