Location
US-CA - Santa Clara
Compensation
$190k–$285k USD
Posted
1 months ago
Market range · function + seniority
p25 · target · p75 · n=216
Posted $285k · in the market band
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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Central Engineering (CE) organization develops the industry’s most advanced High-Speed SerDes (HSS) IPs, covering a broad range of applications including cloud data center, AI/ML infrastructure, 5G wireless, automotive, storage, and optical interconnects. Central System Engineering (CSE), a key function within CE, is responsible for validation, characterization, and application engineering support of high-speed SerDes and analog macros for electrical and optical applications. The team also develops data communication system hardware and software infrastructure to deliver the highest quality SerDes IP and analog macros across Marvell’s Business Units.What You Can Expect
As Director of Application Engineering, you will lead a team of application engineers responsible for enabling Marvell’s high-speed SerDes IP across internal Business Units and external customers. You will serve as the primary technical authority bridging SerDes IP development and real-world system deployment.
Leadership & Team Management
Build, mentor, and manage a high-performing team of application engineers across multiple sites and time zones - Define team charter, set technical direction, and drive execution against program milestones - Partner with senior managers in CE and Business Units on resource planning, headcount strategy, and budget management
Technical Application Engineering
Lead application engineering support for high-speed SerDes IPs (NRZ and PAM4, up to 224G+) across protocols including PCIe, Ethernet (10G–800G), Fibre Channel, CPRI, and CEI - Drive bring-up, debug, and characterization of SerDes blocks including PLL/CDR, ADC/DAC, TX FFE, RX CTLE/DFE, and signal integrity optimization - Own the development of evaluation kits, reference designs, application notes, white papers, and technical collateral for internal and external use - Provide technical leadership on signal integrity analysis, channel modeling, and compliance testing for high-speed electrical and optical interfaces
Customer & Business Unit Engagement
Act as the senior technical interface between CE SerDes IP and Marvell Business Units (Networking, Storage, Compute, Automotive, Custom ASIC) - Engage directly with key customers and partners on design reviews, system bring-up, and performance optimization - Identify new application opportunities and provide product definition input to Design and Marketing teams - Represent Marvell at industry conferences, standards bodies (IEEE, OIF, PCI-SIG), and customer technical forums
Cross-Functional Collaboration
Collaborate with SerDes design, DSP algorithm, and physical design teams to ensure IP is production-ready and customer-deployable - Work with the SW team to define and deliver APIs and firmware enabling BU integration of CE SerDes in SoC products - Drive alignment on test methodology, compliance frameworks, and customer support processes across the organization
What We're Looking For
5+ years in direct people management and technical leadership
Deep expertise in high-speed SerDes architecture, analog/mixed-signal circuits, and data communication systems (NRZ and PAM4 at 56G, 112G, 224G+)
Strong hands-on background in post-silicon bring-up, lab characterization, and signal integrity — including proficiency with oscilloscopes, BERTs, VNAs, and spectrum analyzers
Solid understanding of high-speed interface protocols and standards: PCIe Gen5/6, 100G/400G/800G Ethernet, Fibre Channel, CPRI, OIF CEI)
Experience with high-speed PCB design, channel simulation (ADS, HSPICE), and compliance testing
Proven ability to lead multi-disciplinary teams and drive results across complex, matrixed organizations
Excellent communication and presentation skills; comfortable engaging with executives, customers, and standards bodies
Ability to travel domestically and internationally as needed (~20%)
Preferred Qualifications
Experience with electro-optical systems and optical transceiver applications
Familiarity with scripting and automation (Python, MATLAB, C/C++) for test and characterization workflows
Background in AI/ML infrastructure or hyperscale data center applications
Prior experience working with or within a semiconductor IP organization
Expected Base Pay Range (USD)
190,280 - 285,000, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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