FPGA Prototype Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

In this role, you will drive early‑stage validation of complex SoC and subsystem designs using FPGA/HAPS platforms across AMD’s next‑generation silicon programs. You will collaborate closely with architecture, RTL design, verification, emulation, firmware, and bring‑up teams to deliver high‑fidelity prototypes that enable software development, performance studies, and system integration long before silicon availability.

This role is ideal for an engineer who enjoys hands‑on bring‑up, debug, and system‑level problem solving across hardware, firmware, and validation domains.

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

 

KEY RESPONSIBILITIES:

 

HAPS/FPGA Prototyping & SoC Mapping

• Partition large SoC RTL for multi‑FPGA platforms (Synopsys HAPS or equivalent).
• Perform synthesis, place‑and‑route, timing closure, and resource optimization for FPGA builds.
• Develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles.
• Integrate custom transactors, high‑speed interfaces, and debug instrumentation.

Platform Bring‑Up & Validation

• Bring up prototypes in lab environments, including clocks/resets, DDR, PCIe, networking, and custom high‑speed IP.
• Validate system functionality by running architectural tests, diagnostics, directed tests, and firmware.
• Enable and support pre‑silicon software development (drivers, OS bring‑up, bootloader work).

Debug & Issue Resolution

• Drive debug of functional, timing, or tool‑related issues across FPGA, RTL, and test environments.
• Analyze waveform data, HAPS Deep Trace, SystemVerilog assertions, debug probes, and logic analyzers.
• Work across teams (RTL, DV, Emulation, Firmware, Silicon Bring‑up) to root‑cause and resolve issues efficiently.

Cross‑Functional Collaboration

• Partner with design and DV teams to ensure RTL is “prototype‑ready” with appropriate constraints, transactors, and models.
• Collaborate with software teams to identify, prioritize, and execute pre‑silicon use cases.
• Provide feedback to architecture and design teams based on prototyping insights.

 

PREFERRED EXPERIENCE & SKILLS:

 

Technical Skills

• Strong RTL design background using SystemVerilog/Verilog.
• Hands‑on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms.
• Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes‑based links, etc.
• Familiarity with lint/tools (SpyGlass), CDC, timing constraints, and clocking architecture.
• Strong debug skills across RTL, simulation, FPGA, and system setups.

Software / Scripting

• Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.
• Experience integrating C/C++ or embedded firmware into prototyping flows is a plus.

Soft Skills

• Strong problem‑solving skills and ability to work in ambiguous, cross‑domain environments.
• Excellent communication and ability to collaborate across broad multi‑site teams.
• Self‑starter with the ability to drive issues to closure.

NICE‑TO‑HAVES (OPTIONAL)

• Experience working with large multi‑FPGA prototyping (>10 FPGAs).
• Track record enabling early software stacks (Linux kernel, drivers, boot firmware).
• Familiarity with emulation acceleration, hybrid simulation, or co‑modeling.

ACADEMIC REQUIREMENTS

Bachelor’s degree in electrical/computer engineering or related field, Masters preferred

 

#LI-RF1

 

This role is not eligible for VISA sponsorship.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE:

In this role, you will drive early‑stage validation of complex SoC and subsystem designs using FPGA/HAPS platforms across AMD’s next‑generation silicon programs. You will collaborate closely with architecture, RTL design, verification, emulation, firmware, and bring‑up teams to deliver high‑fidelity prototypes that enable software development, performance studies, and system integration long before silicon availability.

This role is ideal for an engineer who enjoys hands‑on bring‑up, debug, and system‑level problem solving across hardware, firmware, and validation domains.

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

 

KEY RESPONSIBILITIES:

 

HAPS/FPGA Prototyping & SoC Mapping

• Partition large SoC RTL for multi‑FPGA platforms (Synopsys HAPS or equivalent).
• Perform synthesis, place‑and‑route, timing closure, and resource optimization for FPGA builds.
• Develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles.
• Integrate custom transactors, high‑speed interfaces, and debug instrumentation.

Platform Bring‑Up & Validation

• Bring up prototypes in lab environments, including clocks/resets, DDR, PCIe, networking, and custom high‑speed IP.
• Validate system functionality by running architectural tests, diagnostics, directed tests, and firmware.
• Enable and support pre‑silicon software development (drivers, OS bring‑up, bootloader work).

Debug & Issue Resolution

• Drive debug of functional, timing, or tool‑related issues across FPGA, RTL, and test environments.
• Analyze waveform data, HAPS Deep Trace, SystemVerilog assertions, debug probes, and logic analyzers.
• Work across teams (RTL, DV, Emulation, Firmware, Silicon Bring‑up) to root‑cause and resolve issues efficiently.

Cross‑Functional Collaboration

• Partner with design and DV teams to ensure RTL is “prototype‑ready” with appropriate constraints, transactors, and models.
• Collaborate with software teams to identify, prioritize, and execute pre‑silicon use cases.
• Provide feedback to architecture and design teams based on prototyping insights.

 

PREFERRED EXPERIENCE & SKILLS:

 

Technical Skills

• Strong RTL design background using SystemVerilog/Verilog.
• Hands‑on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms.
• Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes‑based links, etc.
• Familiarity with lint/tools (SpyGlass), CDC, timing constraints, and clocking architecture.
• Strong debug skills across RTL, simulation, FPGA, and system setups.

Software / Scripting

• Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.
• Experience integrating C/C++ or embedded firmware into prototyping flows is a plus.

Soft Skills

• Strong problem‑solving skills and ability to work in ambiguous, cross‑domain environments.
• Excellent communication and ability to collaborate across broad multi‑site teams.
• Self‑starter with the ability to drive issues to closure.

NICE‑TO‑HAVES (OPTIONAL)

• Experience working with large multi‑FPGA prototyping (>10 FPGAs).
• Track record enabling early software stacks (Linux kernel, drivers, boot firmware).
• Familiarity with emulation acceleration, hybrid simulation, or co‑modeling.

ACADEMIC REQUIREMENTS

Bachelor’s degree in electrical/computer engineering or related field, Masters preferred

 

#LI-RF1

 

This role is not eligible for VISA sponsorship.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.