Senior DFT Engineer, Test Infrastructure, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Test Engineer, you will work closely with various teams within the design process with other engineers to deliver the confidence needed in the design of the chip. You will collaborate with the Functional Verification team to develop Design for Testing (DFT) environments, drive DFT strategy, and ensure our DFT solutions are properly verified for all usage scenarios.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Engage with DFT and Design teams at early design stage to define requirements for ATE tests and manufacturing test flow.
  
• Generate and verify ATE patterns, including debug level, production level, characterization, High Voltage Screen (HVS), High-Temperature Operating Life (HTOL), Electrical Stress on Environment (ESOE) etc.
• Run pattern playbacks (VTPSIM) on all delivered patterns prior to silicon arrival to ensure high quality of pattern delivery.
  
• Own pattern translations, and integrate DFT verification into the overall ASIC design flow.
  
• Prepare silicon debug verification strategy, test plan, and readiness for testers. Participate in post-manufacturing silicon bring-up tasks.
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with DFT features (e.g., Joint Test Action Group (JTAG)/Memory Built-In Self-Test (MBIST)/Automatic Test Pattern Generation (ATPG)/High-Speed Input/Output (HSIO)), verification, functional validation.
• Experience with one of the scripting languages: Python, Perl, or TCL.
• Experience with ATE platforms (e.g., Teradyne UltraFlex or Advantest).
• Experience with SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 10 years of experience in test engineering or product engineering.
  
• Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or memory BIST test development and repair scheme implementation, including BISR/BIRA.
• Experience in testing Intellectual Property (IP) such as Phase-locked Loops (PLL), Process Voltage Temperature (PVT) sensors, thermal diodes, Process Monitor Ring Oscillator (PMRO), droop detector, aging sensor, and eFuse.
• Experience with PCIE, Double Data Rate (DDR) and HBM testing.