SMTS Design Verification Engineer

Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Design Verification Engineer, you will own pre-silicon functional verification for a high-speed interface chip program. Working on a small, senior team spanning analog design, layout, silicon characterization, and digital design, you will build and execute the verification environment that gives the team confidence in the RTL before silicon is committed.

This is a full-ownership DV role. You will write the DV plan, build the testbench infrastructure, develop directed and constrained-random tests, close coverage, and support the transition from simulation to post-silicon bring-up. The program integrates a fully custom analog PHY alongside soft IP functions including Error Counting, Eye Monitor control, and I2C management interface — providing a technically interesting and varied verification scope well beyond standard digital block verification.

A distinctive aspect of this role is the opportunity — and expectation — to stay engaged through post-silicon bring-up. Your simulation environments, coverage models, and debug waveforms will be directly leveraged in the lab during chip characterization. This is a foundational hire for a growing program, and strong execution early is expected to lead to follow-on projects of increasing scope, team size, and verification complexity.

Responsibilities

• DV Planning: Develop and maintain the full-chip DV plan covering all soft IP blocks and top-level integration; define coverage targets, test priorities, and sign-off criteria in alignment with the Chip Lead.

• Testbench Development: Build and maintain UVM/SystemVerilog verification environments for all key design blocks including I2C and register interface, PRBS-based Error Counting logic, Eye Monitor control state machine, PHY configuration and control register file (CSR / APB or equivalent), and top-level chip integration and block interconnect.

• Test Development: Write directed tests for corner cases and protocol compliance; develop constrained-random test scenarios with appropriate coverage models; achieve and document functional and code coverage closure.

• Assertion-Based Verification: Implement SystemVerilog Assertions (SVA) for critical control sequences, protocol compliance, and reset/initialization behavior in coordination with the Chip Lead.

• Formal Verification: Apply formal property checking (JasperGold or VC Formal) where applicable — CSR correctness, CDC properties, reset verification.

• Regression Management: Build and maintain regression infrastructure; triage failures, root-cause issues to RTL or testbench, and track bug closure through the design team.

• Post-Silicon Support: Provide debug waveforms, expected behavior documentation, and test vectors to support ATE development and lab bring-up in coordination with the Lab Guru.

• DV Documentation: Maintain verification plan, coverage closure reports, and test methodology documentation to support program continuity and follow-on chip development.

Basic Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field

• 6–12 years of functional verification experience in a UVM/SystemVerilog environment

• Demonstrated experience building UVM testbench environments from scratch — not just maintaining or extending existing infrastructure

• Experience verifying serial management interface blocks — I2C, SPI, APB, AHB, or equivalent

• Strong coverage-driven verification methodology — functional coverage modeling, code coverage analysis, and coverage closure documentation

• Solid debugging skills across simulation waveforms and RTL — ability to distinguish RTL bugs from testbench issues quickly and efficiently

• Comfortable working on a small team with a high degree of individual ownership and accountability

Preferred Qualifications

• Experience with formal property verification (JasperGold, VC Formal, or equivalent) for block-level sign-off

• Familiarity with PHY functional modeling or behavioral simulation, including use of vendor-supplied behavioral models or BFMs in a mixed-signal simulation context

• Experience with real-number modeling (RNM) or Verilog-AMS behavioral models for analog block abstraction in digital simulation environments

• Familiarity with PRBS pattern generation and error detection verification — understanding the algorithmic behavior being verified, not just the bus protocol

• Post-silicon validation experience — candidates who have carried verification knowledge into the lab and supported bring-up and debug on real silicon are strongly preferred

• Experience developing ATE test vectors or correlating simulation results to production test programs

• Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart