Sr Design Verification Engineer/Architect, HBM

The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry.

Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise.

Responsibilities:

• Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs
• Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions
• Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disciplinary knowledge across custom digital and RTL2GDS flows
• Evaluate and debug pre-silicon and post-silicon issues in current HBM products, and contribute to exploration of new HBM verification architectures

Minimum Qualifications:

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field
• 4+ years of relevant verification engineering experience, including over 3 years in digital (Verilog), analog (FastSpice), or mixed-signal verification (co-sims or real number modeling)
• Over 2 years working in custom design verification (schematic-based) or RTL design verification flows
• Ability to independently evaluate technical issues and define solutions, with good verbal and written communication skills

Preferred Qualifications:

• Master's in Electrical Engineering, Computer Engineering, or related field, or equivalent experience, accompanied by more than 6 years in verification engineering roles
• One or more patents, trade secrets, or publications showcasing innovation and problem-solving in verification solutions
• Over 2 years in memory products using JEDEC specifications (preferably HBM), with experience building or improving verification flows