Memory System Architect, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your technical expertise in design and uArch to create the most advanced power- and performance-efficient mobile coherent systems. Your work will have a direct impact on the performance, efficiency, and innovation of our next-generation devices. You will work with hardware designers and validation teams to build and test exceptional hardware architectures. As part of this work, you will participate in the development of technology in the memory system and the filing of associated patents.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Explore and evaluate different uArch and design choices for power- and performance-efficient coherent and non-coherent memory systems.
• Author hardware uArch specification for next-generation coherent and non-coherent memory systems.
• Analyze performance and power trade-offs.
• Work with hardware design, verification, emulation, and validation teams to build and test the hardware architecture.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in micro-architecture and design of ASIC blocks.
• Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), caches, Memory Management Units (MMUs), or coherent fabrics.
• Experience in micro-architecture/design performance analysis, tools, and simulators.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• Experience in building build time configurable designs.
• Knowledge in one or more of these areas: coherent interconnects, caches, memory systems.
• Knowledge of Hardware Description Languages (HDL) such as SystemVerilog or Verilog.