Location
AUSTIN
Posted
Today
Market range · company + function + seniority
p25 · target · p75 · n=13
Tailor your résumé to this role in 30 seconds.
Free account · ATS keyword check · per-job bullet rewrite by Claude.
At Cadence, you have the opportunity to work with the dynamic and tenacious team solving some of the most complicated challenges in chip power integrity and thermal analysis. We are looking for people that are willing to push the boundaries of innovation to deliver highest quality solutions to our customers.
If tenacity, passion to innovate, determination to collaborate effectively, and win as a team are the attributes that define you, then you have a home in our team solving Power Integrity problems.
Ideal candidate should have:
Strong ability to solve electrical and electronic circuits.
Excellent knowledge on how power, IR, and EM analyses impact chip planning to IR/EM sign-off.
Fundamental understanding of interconnect modeling, package analysis, and die modeling.
Ability to write and debug automation code in Python or Tcl.
Solid grasp on foundational algorithms to solve numerical and graph problems.
Understanding of how EDA and Semiconductor industry eco-system works.
Alacrity to be an excellent team player.
More open roles at Cadence Design Systems
Hiring velocity, headcount trend, and every open posting on one page.
Open postings ranked by description similarity — useful if this role isn't quite right.