Senior Staff SoC Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. The Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Marvell is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

What You Can Expect

The Senior Staff SoC Design Engineer role focuses on SoC microarchitecture, RTL design, and full-chip integration for high-performance designs. The position involves implementing and integrating complex IP across subsystems, ensuring correct functionality while meeting performance, power, and area (PPA) targets at the SoC level. Responsibilities span the full front-end design flow — from architecture and specification through RTL development, integration, and design sign-off — in close collaboration with verification, physical design, and architecture teams.

• Define microarchitecture and develop SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic such as reset, clocking, and power management.
• Integrate processor clusters, memory controllers (HBM/DDR), and high-speed interfaces with a focus on interface definition, data flow, and system-level behavior.
• Collaborate with verification teams to review test plans, support functional debug, and help close coverage gaps during development.
• Run standard design checks such as lint and CDC/RDC, define timing constraints, and work with synthesis and physical design teams to ensure the design meets implementation requirements.
• Coordinate with IP, SerDes, and analog teams to integrate complex interfaces and resolve subsystem-level issues. Exposure to emerging interconnect standards such as UCIe and UALink is preferred.
• Contribute to design methodology, improve integration workflows, and provide technical guidance to other engineers.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Proven experience delivering complex SoCs to tape-out and working across subsystem boundaries.
• Strong RTL design skills in SystemVerilog and hands-on experience with SoC integration and debug.
• Familiarity with AMBA protocols (AXI) and SoC interconnect architectures, along with clock/reset design, CDC, and timing constraints.
• Understanding of how RTL decisions impact physical implementation.
• Experience with scripting (Python or Tcl) for automation.

Expected Base Pay Range (USD)

134,390 - 201,300, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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