CPU Implementation Engineer

APPLE INC has the following available in Austin, Texas. Perform block-level and top-level EMIR (Electromigration and IR Drop) analysis to identify electrical weaknesses in the power delivery network and ensure design reliability for high performance compute blocks. Conduct power grid design, optimization, and verification using industry-standard physical design (PNR) tools, ensuring robust power delivery and minimal voltage drop across the design. Develop and apply custom scripts in Python and TCL to automate EMIR, SIGEM (Signal EM), and reliability analysis workflows, enabling efficient debugging and large-scale data processing. Investigate and debug high IR drop and EM violations by tracing metal layers, via structures, and current paths, collaborating with physical design teams to suggest layout improvements. Work closely with CAD and EDA vendors to validate tool results, resolve tool-related issues, and incorporate enhancements for accurate EMIR/SIGEM signoff. Collaborate with methodology and implementation teams to support corner-case analysis, refine design guidelines, and ensure alignment on timing, routing, and physical constraints. Provide detailed design reviews and documentation for signoff, highlighting analysis outcomes, coverage metrics, and any risk areas requiring further optimization. Coordinate with SoC-level integration teams to ensure successful block delivery, maintain alignment on power integrity goals, and meet project milestones and tape-out schedules. 40 hours/week.

Master's degree or foreign equivalent in Computer Engineering, or related field.
Experience and/or education must include:
Experience with top level and block level IR drop analysis with static and dynamic vectors in digital silicon circuits
Experience with signal and power electromigration related reliability analysis in digital silicon circuits
Debugging high IR drop and EM violations and directing physical design teams on circuit layout improvements
Developing and applying custom scripts in Python and TCL to automate IR, SIGEM, and reliability analysis workflows
Designing power delivery networks in deep submicron silicon technologies from package to active transistor gate level for very large-scale digital silicon designs
Providing detailed design reviews and documentation for tapeout signoff of or EMIR related items in digital design
Understanding of very large-scale digital design construction from Verilog synthesis to design route/closure (also called SAPR or PNR digital design flows)

N/A

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