CPU Core Architecture/RTL Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

 

THE ROLE:

As a Principal Member of Technical Staff CPU Core Architecture/RTL Engineer, you will have an outstanding opportunity to craft a functional unit in AMD’s next-generation core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

 

THE PERSON:

You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. 

 

KEY RESPONSIBILITIES:

• Execute on RTL design and coding for various sections of the processor core pipeline and related logic.
• Collaborate with a team of hardware and software engineers to define the high-level architecture.
• Participate in the definition of microarchitecture of next-generation high-performance processor cores.
• Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts
• Lead teams of designers collaborating on broader features, supervise the work of junior engineers, and drive methodology improvements.

 

PREFERRED EXPERIENCE:

• Verilog RTL development with industry tools in a CPU, SOC or ASIC environment
• Demonstrates expertise in the following: Processor architectureLogic design
• RTL coding experience for a high-speed processor
• Power-saving techniques
• Exposure to physical design and verification methods
• Awareness of synthesis, place and route, and timing closure concepts
• Development experience from clean-sheet design to product tapeout to post-silicon debug
• Proven experience with microarchitecture development, as demonstrated by patents, publications, product features
• Strong problem-solving and debugging skills
• Background in other aspects of ASIC implementation, especially with synthesis flow and static timing analysis
• Knowledge of microprocessor Design-for-Test (DFT) and Design-for-Debug (DFD) logic and issues
• Experience in clocking, reset, power-up sequences and power management
• Experience with x86 or ARM Architecture (ISA)
• Comfort with scripting such as Perl, Shell, and Tcl

ACADEMIC CREDENTIALS:

• Bachelor’s, Master’s, or PhD with industry experience, preferred; degree with emphasis in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture 

LOCATION:

Fishkill, NY

 

This role is not eligible for visa sponsorship.

 

#LI-AJ1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

 

THE ROLE:

As a Principal Member of Technical Staff CPU Core Architecture/RTL Engineer, you will have an outstanding opportunity to craft a functional unit in AMD’s next-generation core. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

 

THE PERSON:

You approach challenges relentlessly with both critical thinking and creativity. You work as part of a team with strong communication and collaboration skills. You have a proven understanding of modern CPU architecture and have ideas and/or drive to make it even better. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. 

 

KEY RESPONSIBILITIES:

• Execute on RTL design and coding for various sections of the processor core pipeline and related logic.
• Collaborate with a team of hardware and software engineers to define the high-level architecture.
• Participate in the definition of microarchitecture of next-generation high-performance processor cores.
• Contribute to design verification, synthesis, power reduction, timing convergence, and floorplan efforts
• Lead teams of designers collaborating on broader features, supervise the work of junior engineers, and drive methodology improvements.

 

PREFERRED EXPERIENCE:

• Verilog RTL development with industry tools in a CPU, SOC or ASIC environment
• Demonstrates expertise in the following: Processor architectureLogic design
• RTL coding experience for a high-speed processor
• Power-saving techniques
• Exposure to physical design and verification methods
• Awareness of synthesis, place and route, and timing closure concepts
• Development experience from clean-sheet design to product tapeout to post-silicon debug
• Proven experience with microarchitecture development, as demonstrated by patents, publications, product features
• Strong problem-solving and debugging skills
• Background in other aspects of ASIC implementation, especially with synthesis flow and static timing analysis
• Knowledge of microprocessor Design-for-Test (DFT) and Design-for-Debug (DFD) logic and issues
• Experience in clocking, reset, power-up sequences and power management
• Experience with x86 or ARM Architecture (ISA)
• Comfort with scripting such as Perl, Shell, and Tcl

ACADEMIC CREDENTIALS:

• Bachelor’s, Master’s, or PhD with industry experience, preferred; degree with emphasis in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture 

LOCATION:

Fishkill, NY

 

This role is not eligible for visa sponsorship.

 

#LI-AJ1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.