Senior Hardware Emulation Engineer, Google

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting ASIC projects.You will help create ASICs representing a significant investment in time and money, and a successful prototyping campaign helps to ensure success of these critical projects. However, as designs continue to increase in size and complexity, emulation becomes even more important in meeting verification and bring-up milestones. You will provide excellent emulation infrastructure and methodologies essential to support these projects.

You will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will compile complex projects targeting our platforms, bring up high-speed interfaces, debug issues across design and infrastructure, and help drive pre-silicon and lab bring-up and validation of our ASIC systems.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Build, compile, and debug full-chip and multi-die System-on-Chip (SoC) RTL models and tests on hardware emulation platforms.
• Bring up external interfaces (e.g., PCIe, HBM, DDR5, UCIe, Ethernet, USB) on emulation platforms using transactors, Accelerated VIPs, and speed bridges.
• Explore verification and emulation methodologies, gather feedback and implement new emulation workflows and CI/CD automation.
• Partner with firmware, system software, and post-silicon validation teams to drive pre-silicon hardware/software co-verification, shift-left software bring-up, and silicon bug reproduction on emulation.
• Support emulation and software team members in debugging hardware, tooling, compile, and runtime issues, and act as a technical interface to emulation vendors.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 8 years of experience with hardware emulation systems (e.g., Palladium, ZeBu, Veloce), model compilation, runtime performance optimization, and methodology enhancements.
• Experience with Verilog/SystemVerilog, C/C++, Python or Perl/TCL scripting, CI/CD automation, and debugging high-speed protocols (e.g., PCIe, HBM, DDR5, UCIe, Ethernet) using waveform tools (e.g., Verdi, SimVision/Indago, GDB).
• Experience interfacing with emulation EDA vendors and internal infrastructure teams to triage compiler, tool, and platform issues and guage emulation throughput.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience across three or more SoC projects/tapeout cycles.
• Experience architecting and bringing up advanced emulation testbench environments (e.g., Transactors/Accelerated VIPs, SpeedBridges/Speed Adapters, Hybrid/Virtual Host platforms, and In-Circuit Emulation).

In most instances, this position requires in-person interviews as part of the hiring process.