DSP Hardware Design Engineer
Location
SAN JOSE
Compensation
$137k–$254k USD
Type
full time
Posted
2 months ago
Market range · company + function + seniority
p25 · target · p75 · n=48
Posted $254k · in the market band
Tailor your résumé to this role in 30 seconds.
Free account · ATS keyword check · per-job bullet rewrite by Claude.
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Position Requirements are:
- MS in EE /Computer Engg. with 5+ years of relevant CPU or DSP design experience.
- Excellent logic design skills as demonstrated by successful CPU/DSP/NPU/Hardware Accelerator implementations/tape-outs.
- Experience in data-path component design is a plus.
- Excellent knowledge of Verilog/SystemVerilog and popular EDA implementation, simulation and verification tools.
- Experience in AI-native logic design, analysis and/or optimization workflows is a plus.
- Good knowledge of computer architecture and pipe-line designs is required.
- Experience in scripting languages. Good knowledge of Perl is required.
- Experience with assembly language programming is a plus.
- Knowledge and interest in commonly used DSP algorithms in audio, speech, image, video and communication domains is a plus
- Understanding of C/C++ compilers is a plus.
- Excellent written and oral communication skills necessary.
- Self-starter, motivated and eager to learn and contribute to the development of state-of-the-art DSP products
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
More open roles at Cadence Design Systems
Hiring velocity, headcount trend, and every open posting on one page.
Similar roles
Open postings ranked by description similarity — useful if this role isn't quite right.
- Senior Staff Digital Design Engineer79% matchMarvell Technology· Irvine, CA; Santa Clara, CA· $136k–$201k USD
- Staff DSP Architect79% matchMarvell Technology· Santa Clara, CA· $120k–$179k USD
- Principal, IC Digital Design Engineer78% matchMarvell Technology· Irvine, CA· $151k–$223k USD
- ASIC Design Engineer76% matchNVIDIA· US, CA, Santa Clara· $116k–$190k USD
- Senior DSP Engineer, ALG, Amazon Leo Government 76% matchAmazon· Northridge, California, USA· $137k–$186k USD
- ASIC Design Verification Engineer, Digital Signal Processing75% matchGoogle· Sunnyvale, CA, USA· $163k–$236k USD