applinity

ASIC Engineer, Design

at Meta

Location

Sunnyvale, CA; Austin, TX

Compensation

$146k–$209k USD

Type

full time

Posted

2 months ago

Save to queue

Market range · company + function + seniority

$204k—$234k—$249k

p25 · target · p75 · n=162

Posted $209k · in the market band

Tailor your résumé to this role in 30 seconds.

Free account · ATS keyword check · per-job bullet rewrite by Claude.

Tailor my résuméApply on company site

Job description

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning, graphics, display, and network acceleration. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Responsibilities

  • Develop micro-architecture, RTL coding, and design verification for complex IPs.
  • Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration.
  • Assist performance/power analysis of the design and help meet power and performance targets.
  • Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test.
  • Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.

Minimum Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
  • Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development
  • Demonstrated communication and collaboration skills Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
  • Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems
  • Experience with Synthesis, Timing Closure and Formal Verification Methodology
  • Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architectures

More open roles at Meta

Hiring velocity, headcount trend, and every open posting on one page.

View Meta profile →
GuideHow to apply to Meta (the 2-to-3 month process, explained)VisaMeta sponsors H-1B — read the guide

Similar roles

Open postings ranked by description similarity — useful if this role isn't quite right.