ASIC Engineer, Implementation

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure behind Meta's AI, data center, and next-generation computing platforms. As a Staff ASIC Implementation Engineer, you will drive the physical implementation and synthesis of complex custom ASICs from RTL to tape-out, shaping the architectural and methodological decisions that define Meta's silicon roadmap. In this role, you will own end-to-end implementation flows, establish best practices across teams, and partner with design, verification, and physical design teams to deliver high-performance, power-efficient silicon at scale.

Responsibilities

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects
• Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks through collaboration with RTL designers and physical design engineers
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles
• Generate SOC floorplans at the chip level, subsystem level, block level and enable block implementation owners to execute on synthesis & physical design
• Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimisation
• Partner with architecture and RTL teams to provide early feedback on design decisions that impact area, power, and timing outcomes
• Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out
• Identify and drive the resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders
• Mentor other engineers on implementation methodology, synthesis best practices, and timing analysis techniques
• Contribute to long-term silicon implementation strategy, evaluating new EDA tools, flows, and technologies to advance Meta's custom chip capabilities

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in ASIC implementation, including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs
• Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus
• Experience defining and managing synthesis constraints including SDC, UPF, and hierarchical design methodologies
• Experience driving timing closure across multi-million gate designs with multiple clock domains and complex timing exceptions
• Experience developing and maintaining implementation automation using scripting languages such as Tcl or Python Experience evaluating and integrating new EDA tools or methodologies into production implementation flows
• Familiarity with physical-aware synthesis and early floorplan co-design techniques to improve PPA outcomes
• Track record of defining implementation sign-off criteria and leading tape-out execution for complex ASIC designs
• Experience with custom ASIC implementation targeting data center, AI accelerator, or high-performance computing applications