Senior Staff CPU Cache Subsystem Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.
• Review and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.
• Deliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.
• Collaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.

Minimum qualifications:

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications:

• Experience with ARM instruction set architecture.
• Experience with mobile CPU subsystem.
• Experience with mobile SOC architecture/integration.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

In most instances, this position requires in-person interviews as part of the hiring process.