Staff CPU RTL Engineer, Silicon
at Google
Location
Austin, TX, USA; Portland, OR, USA; Mountain View, CA, USA
Compensation
$192k–$278k USD
Type
full time
Posted
1 weeks ago
Market range · company + function + seniority
p25 · target · p75 · n=467
Posted $278k · well above market
Tailor your résumé to this role in 30 seconds.
Free account · ATS keyword check · per-job bullet rewrite by Claude.
Job description
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
- Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
- Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with ARM Instruction Set Architecture.
- Experience with SOC design, architect, and integration.
In most instances, this position requires in-person interviews as part of the hiring process.
More open roles at Google
Hiring velocity, headcount trend, and every open posting on one page.
Similar roles
Open postings ranked by description similarity — useful if this role isn't quite right.
- Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU81% matchSamsung Semiconductor· San Jose, California, United States· $163k–$253k USD
- Senior CPU RTL Engineer, Silicon94% matchGoogle· Mountain View, CA, USA; Portland, OR, USA; Austin, TX, USA· $163k–$236k USD· same company
- Senior Staff CPU Cache Subsystem Design Engineer91% matchGoogle· Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA· $240k–$333k USD· same company
- RTL Design Engineer, TPU Compute88% matchGoogle· Sunnyvale, CA, USA; Austin, TX, USA· $138k–$197k USD· same company
- Lead CPU Design Verification Engineer, Silicon87% matchGoogle· Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA· $192k–$278k USD· same company
- Senior RTL Design Engineer, TPU87% matchGoogle· Sunnyvale, CA, USA· $163k–$236k USD· same company